V
MIPS Pipelined processor simulation
Verilog
The processor was designed and simulated using Verilog.
• The processor could just then accept a bunch of instructions save it in its instruction memory
and the processor would just fetch, decode and execute instructions in a 5-stage pipelined way.
• The processor would then use the pipeline registers and the ALU to do the correct operation
based on the instruction OPcode.
• The result would then be saved to a register or to the memory itself based on the instruction
being executed.
Basic operating system simulation (Assembly/C):
• The kernel is first implemented and designed with some interrupts being implemented to handle specific events.
• The file system is then implemented to store and read files by printing the whole content of a file that is saved in the file system implemented and some additional functionalities were also
implemented like terminating a program and launching a program/ process.
• The shell is then programmed in a way to accept users' commands and to execute them by
calling the correct interrupt handler.
• The OS ensured the safety for processes to work in a shared environment so that the OS
could switch from one process to another one while saving all the process status.
• The OS code is then flushed to a virtual floppy disk to be simulated.
• Some Assembly code were used so that the OS would boot from the virtual floppy image used
Microprocessors (Java):
• Tomasulo processor simulation
Computer Graphics (C++/OpenGL):
• Basic graphical maze game using 3d graphics
Embedded Systems (C++/Arduino):
• Air guitar
Android Computer Lab (Android):
• Android media application to play sings within the same hotspot session.